1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a memory device structure in which a trench capacitor and a MOSFET are connected via a diffusion layer and a manufacturing method thereof. The present invention will be applied to, e.g., a dynamic semiconductor memory (DRAM) and a DRAM/logic-embedded device.
2. Description of the Related Art
With recent development of information communication, the high operating speed and the high integration density of various devices have been required in the semiconductor device technical field. Of such devices, a DRAM/logic-embedded device in which a DRAM and logic circuit are integrated into one chip can realize a large-capacity memory and high data transfer speed, and is growing in demand. A recent DRAM/logic-embedded device structure includes a DRAM array region where a buried strap type trench cell is formed, and a logic region where a MOSFET having a salicide structure in gate/source/drain regions is formed.
As described above, the logic region adopts a salicide structure in which a metal silicide layer is formed on the upper surface of a MOSFET gate electrode/drain region/source region. High performance is realized using a thin film for a MOSFET gate oxide film.
To realize a high integration density and high speed also in the DRAM array region, the MOS polysilicon gate of a cell must be shrunk as much as possible, reducing the cell size. Simple shrinkage degrades the cell performance due to the short channel effect.
As a technique of suppressing the short channel described previously, there has been proposed a technique of pocket-implanting impurity which is the same type as that of the semiconductor substrate under a source/drain. However, as in a prior art, when pocket implantation is simply carried out under the source/drain of the cell transistor, a boron concentration of a BS junction becomes high to increase the junction leak. As a result, such an increased junction leak will deteriorate a charge retention characteristic of DRAM.